Multiplexer (MUX) circuits are commonly used in various applications, including digital logic applications, microprocessor applications, data communication applications, and the like. One type of MUX circuit accommodates a large number of input bits and selects one of the input bits as the output. The output is selected using the appropriate amount of select bits. For example, in an 8:1 MUX circuit, three select bits are used to select one of the eight possible input bits for use as the output bit. Similarly, a 32:1 MUX circuit employs five select bits.
Large scale MUX circuits may be arranged in a multistage manner where each stage includes one or more MUX units. For example, an 8:1 MUX circuit can be arranged using seven MUX units arranged in three stages: an initial stage having four MUX units; an intermediate stage having two MUX units; and a final stage having only one MUX unit. According to established conventions, the input bits selected by the MUX units in the initial stage are controlled using one common select bit, the input bits selected by the MUX units in the intermediate stage are controlled with another common select bit, and the input bit selected by the MUX unit in the final stage is controlled with yet another select bit. For very large scale MUX circuits, the fanout (loading) associated with the select bit lines for the different stages can be significantly different. Thus, the propagation delay associated with the operation of the initial stage can become a limiting factor in the overall performance of conventional multistage MUX circuits.